Generally, a highly integrated semiconductor device is fabricated by a series of steps comprising:
forming a conductive thin film such as a metal film or the like as a conductive wiring material and an interlayer dielectric film for insulating between the conductive thin films on an element such as a silicon wafer, and then uniformly applying a photoresist onto the surface of the resultant to provide a photosensitive layer, which is subjected to selective exposure and development to make a desired photoresist pattern; then,
conducting dry etch treatment of the interlayer dielectric film using this photoresist pattern as a mask to form a desired pattern on the thin film; and,
completely removing the photoresist pattern as well as the residue resulting from the dry etch treatment (hereinafter, referred to as a “dry etch residue”) by oxygen plasma ashing, use of a cleaning solution, or the like.
Recently, along with more shrunken design rules, RC delay is becoming to get on top of the limitation of high-speed arithmetic processing. Accordingly, the interlayer dielectric film is making a shift from a silicon oxide film to a low-dielectric-constant interlayer dielectric film (a film with a dielectric constant of less than 3: hereinafter, referred to as a “low-dielectric-constant interlayer dielectric film”). Moreover, when a pattern of 0.2 μm or less is to be formed, a photoresist with a film thickness of 1 μm will result the aspect ratio of the pattern (a ratio obtained by dividing the thickness of the photoresist film by the line width of the photoresist) to be too large, causing problems such as destruction of the pattern. In order to solve this, a hard mask technique is sometimes employed, in which a film of a titanium (Ti) series, a silicon (Si) series or the like (hereinafter, referred to as a “hard mask”) is inserted between the pattern film that is to be actually formed and the photoresist film so as to once transfer the photoresist pattern onto the hard mask by dry etch. Once the photoresist is removed, this hard mask is used as an etch mask to transfer the pattern onto the film that is to be actually formed by dry etch. According to this method, since the gas used upon etching the hard mask is exchangeable with the gas used upon etching the film that is to be actually formed, one can select a gas that ensures selectivity between the photoresist and the hard mask upon etching the hard mask, and a gas that ensures selectivity between the hard mask and the film to be actually etched upon etching the actual film. Therefore, it is advantageous in that a pattern can be formed while causing minimum damage to the actual film.
When the hard mask is removed by oxygen plasma, however, the low-dielectric-constant interlayer dielectric film may be exposed to the oxygen plasma or the like and may be damaged. For example, in a case of forming a pattern by a dual damascene process, a hard mask is removed by oxygen plasma after forming vias and trenches. Upon this removal, the low-dielectric-constant interlayer dielectric film of the vias and trenches is damaged, which causes a problem of significant deterioration of the electric characteristics. Meanwhile, since dry etch residues are attached to the wafer upon removal of the hard mask, the dry etch residues must also be removed at the same time.
Furthermore, since the current density of metal wiring has been increasing due to shrinking, a countermeasure is strongly required against electromigration, i.e., transport of a metal wiring material due to the current through the metal wiring material, which causes a hole in the metal wiring. As such countermeasures, there are methods in which cobalt or a cobalt alloy is formed on copper wiring as described in Non-patent Document 1 (2010 IEEE International Interconnect Technology Conference pp. 93-95), and methods in which cobalt or a cobalt alloy is used as a metal wiring material as described in Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2013-187350).
Accordingly, there has been a need in fabricating a semiconductor device for a method for removing a hard mask and a dry etch residue while suppressing damage to a low-dielectric-constant interlayer dielectric film, cobalt or a cobalt alloy.
Patent Document 2 (International Publication No. WO 2008/114616) proposes a method of cleaning a semiconductor device with a cleaning composition containing hydrogen peroxide, aminopolymethylene phosphonic acids, potassium hydroxide and water.
Patent Document 3 (Japanese Unexamined Patent Application Publication No. 2010-232486) proposes an etch composition having pH greater than 8.5 and comprising at least one selected from the group consisting of ammonia, a compound having an amino group and a compound having a ring structure containing a nitrogen atom, and hydrogen peroxide in an aqueous medium.
Patent Document 4 (Japanese Unexamined Patent Application Publication (translation of PCT) No. 2005-529363) proposes a cleaning composition comprising a polar organic solvent selected from the group consisting of dimethylpiperidone, sulfones and sulfolanes, a base selected from the group consisting of tetraalkylammonium hydroxide, choline hydroxide, sodium hydroxide and potassium hydroxide, a chelator or a metal complexing agent selected from the group consisting of water and trans-1,2-cyclohexanediamine tetraacetic acid, and ethane-1-hydroxy-1,1-diphosphonate and ethylenediamine tetra(methylene phosphonic acid).
Patent Document 5 (Japanese Unexamined Patent Application Publication No. 2003-234307) proposes a method for cleaning a semiconductor device in which an aqueous sulfuric acid solution at 70° C. or higher is used for cleaning so that titanium nitride (TiN) film is removed while cobalt (Co) silicide is not etched.
Patent Document 6 (International Publication No. WO 2007/072727) proposes a residue removing composition for removing dry etch residues having pH of 1-7 and comprising hydrogen peroxide, an azole compound and a stabilizer for hydrogen peroxide.